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Description: Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
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Size: 7183360 |
Author: 独白惠茹 |
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Description: ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM kernel leads to the JTAG interface, can connect the debugger to debug with keil-MDK!)
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Size: 688128 |
Author: ldz13180882132 |
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Description: This project has dependencies in the 'digilent' VHDL library. For your convenience
a local copy of these dependencies are included in the remote_sources directory.
The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup.
The project configures the two cameras on the VmodCAM for maximum resolution
and frame rate, RGB output and video snapshot mode. The DDR memory on-board
the Atlys is used as a frame buffer. The two video feeds from both cameras are
bufferd in the DDR, while the FPGA drives the HDMI out port with either of the
cameras. Switch 7 selects the camera which gets displayed. The resolution of
the cameras (1600x1200) gets cropped to fit the display resolution of 1600x900.
Project built in ISE 13.2, tested in ISE 13.1.
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Size: 13762560 |
Author: domnish |
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Description: In this paper, a FPGA-based step motor driver implementing adjustable subdivision and sine pulse width modulation is introduced. This driving system can solve the high subdivision problem, increase the driving torque and angle resolution, and smooth the motor angle. Employing the bottom-top design method, the circuit was described by the VHDL language, synthesized by Xilinx ISE integrated environment, and simulated by Modelsim in both behavior level and gate level through the PLI interface. According to experiment’s result, this driver has the advantages of easy debugging, high anti-interference ability, larger driving power, low volume and low cost in large scale production.
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Size: 623104 |
Author: jionad123 |
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Description: SRAM VERILOG 实现FPGA控制SRAM的功能。测试可以使用。(SRAM verilog fpga vivado ise quartus.)
Platform: |
Size: 1024 |
Author: hwz |
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